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<title>MTB CAT1 Peripheral driver library: UART TX FIFO Statuses</title>
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<div class="header">
  <div class="summary">
<a href="#define-members">Macros</a>  </div>
  <div class="headertitle">
<div class="title">UART TX FIFO Statuses<div class="ingroups"><a class="el" href="group__group__scb.html">SCB          (Serial Communication Block)</a> &raquo; <a class="el" href="group__group__scb__uart.html">UART (SCB)</a> &raquo; <a class="el" href="group__group__scb__uart__macros.html">Macros</a></div></div>  </div>
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<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p>Macros to check UART TX FIFO status returned by <a class="el" href="group__group__scb__uart__low__level__functions.html#ga76218bc016256d8525c9d779a4c2e9aa">Cy_SCB_UART_GetTxFifoStatus</a> function or assign mask for <a class="el" href="group__group__scb__uart__low__level__functions.html#gabd4607b147b35fbd9c47e89f77aa1f89">Cy_SCB_UART_ClearTxFifoStatus</a> function. </p>
<p>Each UART TX FIFO status is encoded in a separate bit, therefore multiple bits may be set to indicate the current status. </p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga084f44adc0f1fba7bc8cc63f46c8a3e6"><td class="memItemLeft" align="right" valign="top"><a id="ga084f44adc0f1fba7bc8cc63f46c8a3e6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__uart__macros__tx__fifo__status.html#ga084f44adc0f1fba7bc8cc63f46c8a3e6">CY_SCB_UART_TX_TRIGGER</a>&#160;&#160;&#160;(SCB_INTR_TX_TRIGGER_Msk)</td></tr>
<tr class="memdesc:ga084f44adc0f1fba7bc8cc63f46c8a3e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">The number of entries in the TX FIFO is less than the TX FIFO trigger level value. <br /></td></tr>
<tr class="separator:ga084f44adc0f1fba7bc8cc63f46c8a3e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga41c603d23a12693b3b83ece75da39b54"><td class="memItemLeft" align="right" valign="top"><a id="ga41c603d23a12693b3b83ece75da39b54"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__uart__macros__tx__fifo__status.html#ga41c603d23a12693b3b83ece75da39b54">CY_SCB_UART_TX_NOT_FULL</a>&#160;&#160;&#160;(SCB_INTR_TX_NOT_FULL_Msk)</td></tr>
<tr class="memdesc:ga41c603d23a12693b3b83ece75da39b54"><td class="mdescLeft">&#160;</td><td class="mdescRight">The TX FIFO is not full, there is a space for more data. <br /></td></tr>
<tr class="separator:ga41c603d23a12693b3b83ece75da39b54"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafb9a349f995e46583edd9cdc16efc0af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__uart__macros__tx__fifo__status.html#gafb9a349f995e46583edd9cdc16efc0af">CY_SCB_UART_TX_EMPTY</a>&#160;&#160;&#160;(SCB_INTR_TX_EMPTY_Msk)</td></tr>
<tr class="memdesc:gafb9a349f995e46583edd9cdc16efc0af"><td class="mdescLeft">&#160;</td><td class="mdescRight">The TX FIFO is empty, note there may still be data in the shift register.  <a href="#gafb9a349f995e46583edd9cdc16efc0af">More...</a><br /></td></tr>
<tr class="separator:gafb9a349f995e46583edd9cdc16efc0af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a3ee0ae5c71bb071aa99607dc9a456a"><td class="memItemLeft" align="right" valign="top"><a id="ga5a3ee0ae5c71bb071aa99607dc9a456a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__uart__macros__tx__fifo__status.html#ga5a3ee0ae5c71bb071aa99607dc9a456a">CY_SCB_UART_TX_OVERFLOW</a>&#160;&#160;&#160;(SCB_INTR_TX_OVERFLOW_Msk)</td></tr>
<tr class="memdesc:ga5a3ee0ae5c71bb071aa99607dc9a456a"><td class="mdescLeft">&#160;</td><td class="mdescRight">An attempt to write to the full TX FIFO. <br /></td></tr>
<tr class="separator:ga5a3ee0ae5c71bb071aa99607dc9a456a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3107a2948b2bff6d81c9eb7f51f2a4d4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__uart__macros__tx__fifo__status.html#ga3107a2948b2bff6d81c9eb7f51f2a4d4">CY_SCB_UART_TX_UNDERFLOW</a>&#160;&#160;&#160;(SCB_INTR_TX_UNDERFLOW_Msk)</td></tr>
<tr class="memdesc:ga3107a2948b2bff6d81c9eb7f51f2a4d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">An attempt to read from an empty transmitter FIFO (hardware reads).  <a href="#ga3107a2948b2bff6d81c9eb7f51f2a4d4">More...</a><br /></td></tr>
<tr class="separator:ga3107a2948b2bff6d81c9eb7f51f2a4d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga84d057ed47751c69902a762585ba4838"><td class="memItemLeft" align="right" valign="top"><a id="ga84d057ed47751c69902a762585ba4838"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__uart__macros__tx__fifo__status.html#ga84d057ed47751c69902a762585ba4838">CY_SCB_UART_TX_DONE</a>&#160;&#160;&#160;(SCB_INTR_TX_UART_DONE_Msk)</td></tr>
<tr class="memdesc:ga84d057ed47751c69902a762585ba4838"><td class="mdescLeft">&#160;</td><td class="mdescRight">All data has been transmitted out of the FIFO, including shifter. <br /></td></tr>
<tr class="separator:ga84d057ed47751c69902a762585ba4838"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab629bcb723aafa472383c9dd24d2e492"><td class="memItemLeft" align="right" valign="top"><a id="gab629bcb723aafa472383c9dd24d2e492"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__uart__macros__tx__fifo__status.html#gab629bcb723aafa472383c9dd24d2e492">CY_SCB_UART_TX_NACK</a>&#160;&#160;&#160;(SCB_INTR_TX_UART_NACK_Msk)</td></tr>
<tr class="memdesc:gab629bcb723aafa472383c9dd24d2e492"><td class="mdescLeft">&#160;</td><td class="mdescRight">SmartCard only: the transmitter received a NACK. <br /></td></tr>
<tr class="separator:gab629bcb723aafa472383c9dd24d2e492"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf463f453c30885d0bd6ae52744bb1449"><td class="memItemLeft" align="right" valign="top"><a id="gaf463f453c30885d0bd6ae52744bb1449"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__uart__macros__tx__fifo__status.html#gaf463f453c30885d0bd6ae52744bb1449">CY_SCB_UART_TX_ARB_LOST</a>&#160;&#160;&#160;(SCB_INTR_TX_UART_ARB_LOST_Msk)</td></tr>
<tr class="memdesc:gaf463f453c30885d0bd6ae52744bb1449"><td class="mdescLeft">&#160;</td><td class="mdescRight">SmartCard only: the transmitter lost arbitration. <br /></td></tr>
<tr class="separator:gaf463f453c30885d0bd6ae52744bb1449"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="gafb9a349f995e46583edd9cdc16efc0af"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gafb9a349f995e46583edd9cdc16efc0af">&#9670;&nbsp;</a></span>CY_SCB_UART_TX_EMPTY</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define CY_SCB_UART_TX_EMPTY&#160;&#160;&#160;(SCB_INTR_TX_EMPTY_Msk)</td>
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</div><div class="memdoc">

<p>The TX FIFO is empty, note there may still be data in the shift register. </p>

</div>
</div>
<a id="ga3107a2948b2bff6d81c9eb7f51f2a4d4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3107a2948b2bff6d81c9eb7f51f2a4d4">&#9670;&nbsp;</a></span>CY_SCB_UART_TX_UNDERFLOW</h2>

<div class="memitem">
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      <table class="memname">
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          <td class="memname">#define CY_SCB_UART_TX_UNDERFLOW&#160;&#160;&#160;(SCB_INTR_TX_UNDERFLOW_Msk)</td>
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<p>An attempt to read from an empty transmitter FIFO (hardware reads). </p>

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